A Comprehensive Approach to Low-Power UVM Verification Using Power-Aware Coverage Models

The semiconductor industry has been pushing for designs that use less energy and work better. Now, because of this, there are ways to design things that use less energy. But still, the checking of these designs is hard due to the complications introduced by features such as dynamic voltage and frequency scaling (DVFS), power gating, and multi-power domains. One of the common ways of checking a system is the Universal Verification Methodology. This is now the most common way in which SoCs are checked. Of course, power is an issue in traditional UVM environments, but they do not have built-in support for it.

This article is about how to enhance the verification capabilities of the low-power UVM environments using power-aware coverage models. Our scheme uses the meaning of Unified Power Format and captures power-aware coverage metrics in concord with power intent and changes in the power state. We use a case study of low-power SoC design that can be used in more than one place to test the proposed framework. We outline how our method facilitates the checking of the coverage, finding important verification gaps, and verifying power intent.

By running numerous simulations and coverage outcomes, it is demonstrated that power-aware UVM environments enhance significant confidence in the precision of the low-power designs and reduce errors in verification. The paper concludes by talking about how combining low-power assertions, machine learning-enhanced coverage closure, and formal verification could help future progress.

UVM Low-Power Verification Power-Aware Coverage Unified Power Format (UPF) DVFS Power Gating Multi-Power Domains Functional Verification Coverage Closure Power Intent Validation

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